A field-programmable gate array (FPGA) may be used as an accelerator for some processes (e.g., image processing, machine learning, software defined networking, etc.) because of the high performance and high performance per watt of the FPGA. Hardware description language (HDL) (e.g., Very high speed integrated circuit HDL (VHDL), Verilog, etc.) may be used to program such processes. HDL is synthesized into netlist, which is placed and routed to generate a hardware bitstream. The bitstream is flashed into the FPGA to generate a customized accelerator. In some examples, FPGA may be programmed using an American National Standards Institute (ANSI) C-based language (e.g., Open Computing Language (OpenCL)), in which the C-based code is converted into a HDL kernel that may be compiled by the FPGA. Both HDL and OpenCL are static languages in which once the kernel is compiled, it will be loaded and executed by the FPGA during runtime without any runtime changes.
The figures are not to scale. Wherever possible, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts.